Field
This disclosure relates generally to integrated circuits, and more particularly, to covering all addresses in a memory array while minimizing transition time between addresses during built-in self test.
Related Art
Memory devices include an array of memory cells that are addressed on a row by column basis. Many memory devices include built-in self test (BIST) logic that is used to determine whether the memory cells in the array are functioning properly. Due to the large number of cells in the array, the time required to address and test each cell individually is prohibitively long, so a subset of the cells is typically tested instead. If all of the cells in the chosen subset pass BIST, it is assumed that the remaining cells will also pass BIST. Under some circumstances, it is desirable to test all of the cells in the array, while minimizing the time required to test the memory cells.